Conventional vertical MOSFET devices are constructed to operate within certain predefined narrow limits. For instance, in a conventional device of a specific break-down voltage, the drift region carrier concentration cannot be increased beyond a maximum concentration established by the avalanche electric field. Further, it may not be desirable to increase the dopant concentration to near its maximum limit to reduce the on-resistance of the device because such a dopant increase will also reduce the break-down voltage of the device. Conversely, the drift region carrier concentration cannot be reduced to increase the breakdown voltage without also increasing the on-resistance of the device. Considered in an alternate light, the ideal on-resistance of a conventional device is equal to the length of the drift region divided by the product of mobility, carrier concentration and electron charge. Inasmuch as the avalanche electric field is approximately inversely proportional to the carrier concentration raised to the half power, the on-resistance can be considered proportional to the length of the drift region divided by carrier concentration raised to the 1.5 power. Further, inasmuch as the length of the drift region is proportional to the breakdown voltage, and because the carrier concentration is inversely proportional to the voltage, the ideal on-resistance of a conventional device can be considered proportional to the breakdown voltage, V.sub.B, raised to the 2.5 power. Thus, in a one dimensional analysis, the ideal on-resistance of a conventional vertical channel device can be expressed as: ##EQU1## where N.sub.o is the doping concentration within the drift region and L.sub.o is the depth or length of the drift region.
The above one dimensional conventional on-resistance proportional equation can be derived form the one dimensional expressions of the Gauss's law and the voltage equation for conventional devices which are expressed immediately below as equations (2) and (3), respectively. ##EQU2## where .mu. is the mobility of the semiconductor material, .epsilon. is the permitivity constant of the semiconductor material and E.sub.AV is the avalanche electric field for a drift region doped at N. Thus, in conventional MOSFET devices of which vertical channel devices are a prime example, many of the operating parameters are interrelated and the operating characteristic of a conventional device, such as the breakdown voltage or on-resistance can be varied only over a narrow range of values.
A conventional vertical channel MOSFET device is shown in cross section in FIG. 1 in which a vertical trench, which may contain an insulated gate, extends through an N+ source region, a P base region and across a blocking junction and a short distance L.sub.t into the drift region of the device. The distance L.sub.t by which the trench overlaps into the drift region is optimally small but is typically in the order of 0.5 microns. Some small overlap is provided to ensure that the trench extends completely across the P base region. If the width of a unit cell of the device is specified as W, the ratio of L.sub.t /W will be very small and typically in the order of 0.05. The gate electrode is terminated as close to the blocking junction as possible to reduce fringing fields at the trench corners which otherwise would reduce the device breakdown voltage and the gate-drain breakdown voltage. Thus, the ratio of L.sub.t /W preferably approaches zero. Further, the thickness of the gate oxide within the trench is minimized to achieve a channel of maximum conductivity for minimum gate voltage. In conventional devices, gate oxide thickness are generally in the order of 100-2000 angstroms and allow a gate bias of approximately 1-10 volts to induce a channel by establishing an inversion layer in the region of the semiconductor substrate beneath the gate to render the device conductive in response to the applied gate bias. Gate oxides thicker than 2000 angstroms have not been used in the vertical channel art inasmuch as such a thick oxide would impair the effect of the gate bias, and inhibit the establishment of the requisite inversion layer, or conversely require a larger gate bias to establish the requisite channel conductivity.